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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. e 11/26/03 is62C1024L issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. description the issi is62C1024L is a low power,131,072-word by 8-bit cmos static ram. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce1 is high or ce2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using cmos input levels. easy memory expansion is provided by using two chip enable inputs, ce1 and ce2. the active low write enable ( we ) controls both writing and reading of the memory. the is62C1024L is available in 32-pin plastic sop and tsop (type 1) packages. functional block diagram 128k x 8 low power cmos static ram features ? high-speed access time: 35, 70 ns low active power: 450 mw (typical) low standby power: 150 w (typical) cmos standby output enable ( oe ) and two chip enable ( ce1 and ce2) inputs for ease in applications fully static operation: no clock or refresh required ttl compatible inputs and outputs single 5v (10%) power supply a0-a16 ce1 oe we 128k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 ce2 december 2003
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. e 11/26/03 is62C1024L issi ? truth table mode we we we we we ce1 ce1 ce1 ce1 ce1 ce2 oe oe oe oe oe i/o operation v dd current not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x high-z i sb 1 , i sb 2 output disabled h l h h high-z i cc read h l h l d out i cc write l l h x d in i cc pin configuration 32-pin sop pin descriptions a0-a16 address inputs ce1 chip enable 1 input ce2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output v dd power gnd ground operating range range ambient temperature v dd commercial 0c to +70c 5v 10% industrial ?40c to +85c 5v 10% pin configuration 32-pin tsop (type 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vdd a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 issi 62C1024L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we ce2 a15 vdd nc a16 a14 a12 a7 a6 a5 a4 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. e 11/26/03 is62C1024L issi ? absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 5.0v. dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 2.1 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.5 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?2 2 a ind. ?10 10 i lo output leakage gnd v out v dd com. ?2 2 a ind. ?10 10 notes: 1. v il = ?3.0v for pulse width less than 10 ns.
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. e 11/26/03 is62C1024L issi ? read cycle switching characteristics (1) (over operating range) -35 -70 symbol parameter min. max. min. max. unit t rc read cycle time 35 ? 70 ? ns t aa address access time ? 35 ? 70 ns t oha output hold time 3 ? 3 ? ns t ace 1 ce1 access time ? 35 ? 70 ns t ace 2 ce2 access time ? 35 ? 70 ns t doe oe access time ? 10 ? 35 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzoe (2) oe to high-z output 0 10 0 25 ns t lzce 1 (2) ce1 to low-z output 3 ? 10 ? ns t lzce 2 (2) ce2 to low-z output 3 ? 10 ? ns t hzce (2) ce1 or ce2 to high-z output 0 10 0 25 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. power supply characteristics (1) (over operating range) -35 ns -70 ns symbol parameter test conditions min. max. min. max. unit i cc v dd dynamic operating v dd = max., ce = v il com. ? 100 ? 70 ma supply current i out = 0 ma, f = f max ind. ? 110 ? 80 i sb 1 ttl standby current v dd = max., com. ? 10 ? 10 ma (ttl inputs) v in = v ih or v il , ce1 v ih , ind. ? 15 ? 15 or ce2 v il , f = 0 i sb 2 cmos standby v dd = max., com. ? 500 ? 500 a current (cmos inputs) ce1 v dd ? 0.2v, ind. ? 750 ? 750 ce2 0.2v, v in v dd ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. e 11/26/03 is62C1024L issi ? data valid t aa t oha t oha t rc dout address ac waveforms read cycle no. 1 (1,2) ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 5 ns input and output timing 1.5v and reference level output load see figures 1a and 1b ac test loads figure 1a. figure 1b. 480 ? 100 pf including jig and scope 255 ? output 5v 480 ? 5 pf including jig and scope 255 ? output 5v
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. e 11/26/03 is62C1024L issi ? write cycle switching characteristics (1,3) (over operating range, standard and low power) -35 -70 symbol parameter min. max. min. max. unit t wc write cycle time 35 ? 70 ? ns t sce 1 ce1 to write end 25 ? 60 ? ns t sce 2 ce2 to write end 25 ? 60 ? ns t aw address setup time to write end 25 ? 60 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe (4) we pulse width 25 ? 50 ? ns t sd data setup to write end 20 ? 30 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 10 ? 25 ns t lzwe (2) we high to low-z output 3 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce1 low, ce2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to t he rising or falling edge of the signal that terminates the write. 4. tested with oe high. notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce1 = v il , ce2 = v ih . 3. address is valid prior to or coincident with ce1 low and ce2 high transitions. read cycle no. 2 (1,3) t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzce address oe ce1 ce2 dout
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. e 11/26/03 is62C1024L issi ? write cycle no. 2 ( ce1 ce1 ce1 ce1 ce1 , ce2 controlled) (1,2) notes: 1. the internal write time is defined by the overlap of ce1 low, ce2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to t he rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe = v ih . ac waveforms write cycle no. 1 ( we we we we we controlled) (1,2) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 ce2 we dout din high-z data undefined data-in valid t wc t sce1 t sa t ha t sce2 t pwe (4) t aw t hzwe t sd t hd t lzwe address din ce1 ce2 we dout
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. e 11/26/03 is62C1024L issi ? data retention switching characteristics symbol parameter test condition min. typ. max. unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 3.0v, ce1 v dd ? 0.2v com. ? 45 250 a ind. ? 60 400 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns data retention waveform ( ce1 ce1 ce1 ce1 ce1 controlled) data retention waveform (ce2 controlled) vdd ce1 vdd - 0.2v t sdr t rdr v dr ce1 gnd 4.5v 2.2v data retention mode vdd ce2 0.2v t sdr t rdr v dr 0.4v ce2 gnd 4.5v 2.2v data retention mode
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. e 11/26/03 is62C1024L issi ? issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0c to +70c speed (ns) order part no. package 35 is62C1024L-35q plastic sop 35 is62C1024L-35t tsop, type 1 70 is62C1024L-70q plastic sop 70 is62C1024L-70t tsop, type 1 industrial range: ?40c to +85c speed (ns) order part no. package 35 is62C1024L-35qi plastic sop 35 is62C1024L-35ti tsop, type 1 70 is62C1024L-70qi plastic sop 70 is62C1024L-70ti tsop, type 1
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/13/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 450-mil plastic sop package code: q (32-pin) d seating plane b e c 1 n e1 a1 a e l s millimeters inches symbol min. max. min. max. no. leads 32 a ? 3.00 ? 0.118 a1 0.10 ? 0.004 ? b 0.36 0.51 0.014 0.020 c 0.15 0.30 0.006 0.012 d 20.14 20.75 0.793 0.817 e 13.87 14.38 0.546 0.566 e1 11.18 11.43 0.440 0.450 e 1.27 bsc 0.050 bsc l 0.58 0.99 0.023 0.039 0 10 0 10 s ? 0.86 ? 0.034 notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/13/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop-type i package code: t (32-pin) d seating plane b e c 1 n e a1 a s h l notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches symbol min. max. min. max. no. leads 32 a ? 1.20 ? 0.047 a1 0.05 0.25 0.002 0.010 b 0.17 0.23 0.007 0.009 c 0.12 0.17 0.005 0.007 d 7.90 8.10 0.311 0.319 e 18.30 18.50 0.720 0.728 h 19.80 20.20 0.780 0.795 e 0.50 bsc 0.020 bsc l 0.40 0.60 0.016 0.024 0 8 0 8 s 0.25 ref 0.010 ref

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